View LTC3536_7805887.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC3536 1 3536fa typical a pplica t ion fea t ures descrip t ion 1a low noise, buck-boost dc/dc converter the ltc ? 3536 is an extended v in range, fixed frequency, synchronous buck-boost dc/dc converter that operates from input voltages above, below or equal to the regulated output voltage. the topology incorporated in the LTC3536 provides low noise operation, making it ideal for rf and precision measurement applications. the device can produce up to 1a of continuous output current, and it includes two n-channel and two p-channel mosfet switches. switching frequencies up to 2mhz can be programmed with an external resistor and the oscilla - tor can be synchronized to an external clock. quiescent current is only 32a in burst mode operation, maximizing battery life in portable applications. burst mode operation is user controlled and improves efficiency at light loads. other features include a 1a shutdown current, internal soft-start, overtemperature protection and current limit. the LTC3536 is available in 12-pin thermally enhanced msop and 10-pin (3mm 3mm) dfn packages. efficiency vs input voltage a pplica t ions n regulated output with input voltage above, below or equal to the output v oltage n 1.8v to 5.5v input and output voltage range n 1a continuous output current for v in 3v, v out = 3.3v n 1% output voltage accuracy n low noise buck-boost architecture n up to 95% efficiency n programmable frequency from 300khz to 2mhz n synchronizable oscillator n burst mode ? operation: 32a i q n internal 1ms soft-start n output disconnect in shutdown n shutdown current: 1a n short-circuit protection n small thermally enhanced 12-pin msop and 10-pin (3mm 3mm) dfn packages n wireless inventory t erminals n handheld medical instruments n wireless locators, microphones n supercapacitor backup power supply l , lt, ltc, ltm, burst mode, ltspice, linear technology and the linear logo are registered trademarks and powerpath and no r sense are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. sw1 v in sw2 v out fb 10f 22f 47pf 6.49k v in 1.8v to 5.5v pwm burst vc LTC3536 4.7h 49.9k 1000k 220pf mode/sync shdn rt v out 3.3v 1a for v in 3v 221k 3536 ta01a pgnd sgnd off on input voltage (v) 1.5 50 efficiency (%) 55 65 70 75 100 85 2.5 3.5 4 3536 ta01b 60 90 95 80 2 3 4.5 5 5.5 i load = 1a i load = 200ma
LTC3536 2 3536fa a bsolu t e maxi m u m r a t ings v in , v out , (sv in , pv in ) voltage .................... C 0.3v to 6v sw1, sw2 voltage d c ............................................................ C 0.3v to 6v pu lsed (<100ns) ........................................ C 1.0v to 7v vc, rt, fb, shdn voltage ............................ C 0.3v to 6v mode/sync voltage ................................... C 0.3v to 6v (note 1) top view 11 pgnd dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 vc fb shdn v in v out rt sgnd mode/sync sw1 sw2 t jmax = 125c, v ja = 39.7c/w exposed pad (pin 11) is pgnd, must be soldered to pcb 1 2 3 4 5 6 rt sgnd mode/sync sw1 pgnd sw2 12 11 10 9 8 7 vc fb shdn v in v in v out top view 13 pgnd mse package 12-lead plastic msop t jmax = 125c, v ja = 40c/w exposed pad (pin 13) is pgnd must be soldered to pcb for rated thermal performance and load regulation p in c on f igura t ion e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 3.3v, v out = 3.3v, r t = 100k unless otherwise noted. o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC3536edd#pbf LTC3536edd#trpbf lfzd 10-lead (3mm w 3mm) plastic dfn C40c to 125c LTC3536idd#pbf LTC3536idd#trpbf lfzd 10-lead (3mm w 3mm) plastic dfn C40c to 125c LTC3536emse#pbf LTC3536emse#trpbf 3536 12-lead plastic msop C40c to 125c LTC3536imse#pbf LTC3536imse#trpbf 3536 12-lead plastic msop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ parameter conditions min typ max units input operating range l 1.8 5.5 v output voltage adjust range l 1.8 5.5 v undervoltage lockout threshold v in ramping down v in ramping up l l 1.6 1.67 1.75 1.8 v v feedback voltage 0c < t j < 85c (note 5) C40c < t j < 125c l 0.594 0.591 0.6 0.6 0.606 0.609 v v feedback pin input current (fb) v fb = 0.6v in servo loop, v mode/sync = 0v 50 na quiescent current, burst mode operation v fb = 0.7v, v mode/sync = v in 32 42 a quiescent current, shutdown (i vin ) v shdn = 0v 0.1 1 a operating junction temperature range (notes 2, 3) ............................................ C 40c to 125c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) m se .................................................................. 3 00c
LTC3536 3 3536fa e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3536 is tested under pulsed load conditions such that t j t a . the LTC3536e is guaranteed to meet specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the l tc3536i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 3.3v, v out = 3.3v, r t = 100k unless otherwise noted. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: current measurements are performed when the LTC3536 is not switching. the current limit values measured in operation will be somewhat higher due to the propagation delay of the comparators. note 5: guaranteed by design characterization and correlation with statistical process controls. note 6: guaranteed by correlation and design. parameter conditions min typ max units quiescent current, active (i vin ) v fb = 0.7v, v mode/sync = 0v 800 a input current limit v mode/sync = 0v (note 4) l 2 2.5 a peak current limit v mode/sync = 0v (note 4) 3.4 4 a burst mode peak current limit v mode/sync = v in (note 4) 0.4 0.6 a reverse current limit (note 4) l 0.3 0.55 a nmos switch leakage switch b, c: sw1 = sw2 = 5.5v, v in = 5.5v, v out = 5.5v 0.1 1 a pmos switch leakage switch a, d: sw1 = sw2 = 0v, v in = 5.5v, v out = 5.5v 0.1 1 a nmos switch on-resistance switch b (from sw1 to gnd) (note 6) switch c (from sw2 to gnd) (note 6) 0.11 0.1 pmos switch on-resistance switch a (from v in to sw1) (note 6) switch d (from v out to sw2) (note 6) 0.12 0.145 frequency accuracy r t = 100k l 0.8 1 1.2 mhz frequency accuracy default r t = v in l 0.96 1.2 1.44 mhz internal soft-start time v fb from 0.06v to 0.54v 0.6 0.9 1.2 ms maximum duty cycle percentage of period sw2 is low in boost mode l 88 91 % minimum duty cycle percentage of period sw1 is high in buck mode l 0 % error amplifier avol 90 db error amplifier sink current fb = 1.3v, vc = 1v 250 300 a error amplifier source current fb = 0.3v, vc = 0v 400 480 a mode/sync input logic threshold disable burst mode operation 0.3 1 v mode/sync external synchronization sync level high sync level low l l 1.2 0.4 v v mode/sync synchronization frequency l 0.3 2 mhz mode/sync input current v mode/sync = 5.5v = v in 1 a shdn input logic threshold l 0.3 1 v shdn input current v shdn = 5.5v = v in 1 a
LTC3536 4 3536fa typical p er f or m ance c harac t eris t ics no-load quiescent current in pwm mode operation input current limit vs supply voltage, v out = gnd input current limit vs supply voltage, v out = 3.3v r ds(on) for p-channel switch a r ds(on) for n-channel switch b r ds(on) for n-channel switch c efficiency 3.3v vs load current efficiency li-ion (3v, 3.7v, 4.2v) to 3.3v output no-load quiescent current in burst mode operation (mode = v in ) t a = 25c, v in = v out = 3.3 v unless otherwise noted. load current (a) 0.001 0.01 0.1 1 40 efficiency (%) 50 60 70 80 3536 g01 30 20 10 0 90 100 v in = 1.8v v in = 2.5v v in = 5.5v v in = 1.8v burst v in = 2.5v burst v in = 5.5v burst load current (a) 0.001 0.01 0.1 1 40 efficiency (%) 50 60 70 80 3536 g02 30 20 10 0 90 100 v in = 3v v in = 3.7v v in = 4.2v v in = 3v burst v in = 3.7v burst v in = 4.2v burst input voltage (v) 1.5 input quiescent current (a) 40 45 50 5.5 3536 g03 35 30 20 2.5 3.5 4.5 2 6 3 4 5 25 60 55 v out = 1.8v v out = 3.3v v out = 5.5v input voltage (v) 1.5 input quiescent current (ma) 8 10 12 5.5 3536 g04 6 4 0 2.5 3.5 4.5 2 6 3 4 5 2 14 v out = 3.3v v out = 1.8v v out = 5.5v input voltage (v) 1.5 input current limit (a) 1.4 1.6 1.8 2.0 3.5 3536 g05 1.2 1.0 0.9 0.8 0.7 0.6 1.3 1.5 1.7 1.9 1.1 0.5 2 2.5 3 4 4.5 5 5.5 6 125c 85c 25c ?40c input voltage (v) 1.5 r ds(on) (m) 120 240 260 280 2.5 3.5 4 3536 g07 80 200 160 100 220 60 180 140 2 3 4.5 65 5.5 ?45c 0c 25c 85c 125c input voltage (v) 1.5 r ds(on) (m) 120 240 260 280 2.5 3.5 4 3536 g08 80 200 160 100 220 60 180 140 2 3 4.5 65 5.5 ?45c 0c 25c 85c 125c input voltage (v) 1.5 r ds(on) (m) 120 240 260 280 2.5 3.5 4 3536 g09 80 200 160 100 220 60 180 140 2 3 4.5 65 5.5 ?45c 0c 25c 85c 125c input voltage (v) 1.5 input current limit (a) 2.5 2.7 2.9 3.1 3.5 3536 g06 2.3 2.1 2.0 1.9 1.8 1.7 2.4 2.6 2.8 3.0 2.2 1.6 2 2.5 3 4 4.5 5 5.5 6 125c 85c 25c ?40c
LTC3536 5 3536fa typical p er f or m ance c harac t eris t ics maximum load current in pwm mode vs input voltage 1mhz switching frequency, 4.7h inductor value maximum load current in burst mode operation vs input voltage negative inductor current vs oscillator frequency change in output voltage vs load current for 3.3v output and 3.3v input load step 0a to 1a load step 0ma to 300ma r ds(on) for p-channel switch d feedback voltage oscillator frequency vs r t t a = 25c, v in = v out = 3.3 v unless otherwise noted. input voltage (v) 1.5 r ds(on) (m) 120 240 260 280 2.5 3.5 4 3536 g10 80 200 160 100 220 60 180 140 2 3 4.5 65 5.5 ?45c 0c 25c 85c 125c r t (k) 40 0 oscillator frequency (mhz) 0.4 0.8 1.2 90 140 190 240 3536 g12 290 1.6 2.0 0.2 0.6 1.0 1.4 1.8 340 input voltage (v) 1.5 0 maximum load current (ma) 500 1500 2000 2500 2.5 3.5 4 6 3536 g13 1000 2 3 4.5 5 5.5 v out = 1.8v v out = 3.3v v out = 5.5v input voltage (v) 1.5 0 maximum load current (ma) 50 150 200 250 2.5 3.5 4 6 3536 g14 100 2 3 4.5 5 5.5 300 v out = 1.8v v out = 3.3v v out = 5.5v oscillator frequency (mhz) 0.2 0.60.4 0.8 1.21 1.4 1.6 1.8 2.2 2.4 2 reverse current limit (a) ?1.0 ?0.5 3536 g15 ?1.5 ?2.0 0 v out pulled up to 3.6v v in = 1.8v l = 4.7h load current (ma) 0.001 output voltage regulation (%) 0 1 0.01 0.1 10 1 3536 g16 ?1 ?2 ?3 pwm burst v out 200mv/div i load 500ma/div 100s/div 3536 g17 v in = 3.2v v out = 3.3v v out 200mv/div i load 100ma/div 100s/div 3536 g18 v in = 1.8v v out = 3.3v temperature (c) ? 50 change in voltage from 25c (%) 0.2 0.6 1.0 110 3536 g11 ?0.2 ?0.6 0 0.4 0.8 ?0.4 ?0.8 ?1.0 ? 10? 30 3010 70 90 130 50 150
LTC3536 6 3536fa typical p er f or m ance c harac t eris t ics soft-start start-up in burst mode operation with output precharged start-up in pwm mode operation with output precharged output voltage ripple in pwm mode output voltage ripple in burst mode operation burst mode operation to pwm mode transient t a = 25c, v in = v out = 3.3 v unless otherwise noted. v out 20mv/div v in = 2.5v v out 20mv/div v in = 3.3v v out 20mv/div v in = 5v 2s/div 3536 g19 v out = 3.3v i load = 0.5a v out 50mv/div v in = 5.5v v out 50mv/div v in = 3.3v v out 50mv/div v in = 1.8v 100s/div 3536 g21 v out = 3.3v i load = 25ma c out = 22f l = 4.7h v out 1v/div i load 500ma/div shdn 2v/div 200s/div 3536 g22 v in = 3v v out = 3.3v c out = 22f v out 100mv/div shdn 1v/div 5ms/div 3536 g23 v in = 3v v out = 3.3v c out = 22f i load = 1ma v out 500mv/div shdn 1v/div 500s/div 3536 g24 v in = 3v v out = 3.3v c out = 22f i load = 20ma v out 50mv/div inductor current 200ma/div 50s/div 3536 g20 v out = 3.3v i load = 4ma
LTC3536 7 3536fa p in func t ions (dfn/msop) rt (pin 1/pin 1): oscillator frequency programming input. connect a resistor from rt to gnd to program the internal oscillator frequency. the frequency is given by: f osc (mhz) = 100/r t (k) where r t is in k and f osc is between 0.3mhz and 2mhz. tying the rt pin to v in enables the internal 1.2mhz default oscillator frequency. sgnd (pin 2/pin 2): ground connection for the LTC3536. a ground plane is highly recommended. sensitive analog components terminated at ground should connect to the gnd pin with a kelvin connection, separated from the high current path. mode/sync (pin 3/pin 3): pulse width modulation/burst mode selection and synchronization input. driving mode to a logic 0 state programs fixed frequency, low noise pwm operation. driving mode to logic 1 state programs burst mode operation for highest efficiency at light loads. in burst mode operation, the output current capability is significantly less than what is available in pwm operation. refer to the applications information section of this data sheet for details. frequency synchronization is achieved if a clock pulse is applied to mode/sync. the external clock pulse amplitude must have an amplitude equal or higher than 1.2v and duty cycle from 10% and 90%. the free-running frequency of the LTC3536 oscillator can be programmed slower or faster than the synchronization clock frequency. sw1 (pin 4/pin 4): switch pin. connect to internal power switches a and b. connect one side of the buck-boost inductor to sw1. provide a short wide pcb trace from the inductor to sw1 to minimize voltage transients and noise. sw2 (pin 5/pin 6): switch pin. connect to internal power switches c and d. connect one side of the buck-boost inductor to sw2. provide a short wide pcb trace from the inductor to sw2 to minimize voltage transients and noise. v out (pin 6/pin 7): output voltage. this pin is the power output for the regulator. a low esr capacitor should be placed between this pin and the ground plane. the capaci- tor should be placed as close to this pin as possible and have a short return path to ground. v in (pin 7/pins 8, 9): power input for the converter. a low esr 10f or larger bypass capacitor should be connected between this pin and ground. the capacitor should be placed as close to this pin as possible and have a short return path to ground. shdn (pin 8/pin 10): enable input. a logic 1 on shdn activates the buck-boost regulator. a logic 0 on shdn deactivates the buck-boost regulator. fb (pin 9/pin 11): output voltage programming feedback divider input. the regulator output voltage is programmed by the voltage divider connected to fb. the buck-boost output is given by the following equation: v out = 0.6v ? (1 + r top /r bot ) (v) where r bot is a resistor connected between fb and ground and r top is a resistor connected between fb and v out . the buck-boost output voltage can be adjusted from 1.8v to 5.5v. vc (pin 10/pin 12): error amplifier output. frequency compensation components are connected between vc and fb to provide stable operation of the converter. refer to the applications information section of this data sheet for design details. pgnd (exposed pad pin 11/pin 5, exposed pad pin?13): power ground. the exposed pad must be soldered to the pcb and electrically connected to ground through the shortest and lowest impedance connection possible.
LTC3536 8 3536fa b lock diagra m 1.75v ? + ? + pwm and output phasing gate drivers and anticross conduction l peak current limit 3.4a uvlo osc burst mode control run logic sync sleep sgnd swb swc reverse current limit current limit error amp sw1 sw2 swd v out 1.8v to 5.5v v in 1.8v to 5.5v pgnd ?0.4a swa ? + ? + 2.5a soft-start 0.6v fb r top r bot 3635 bd r t 1 = on 0 = off c out ? + + rt mode/sync 1 = burst 0 = pwm vc c fb shdn c in +
LTC3536 9 3536fa o pera t ion i ntroduction the LTC3536 is a monolithic buck-boost converter that can operate with input and output voltages from as low as 1.8v to as high as 5.5v . a proprietary switch control algorithm allows the buck-boost converter to maintain output voltage regulation with input voltages that are above, below or equal to the output voltage. transitions between these operating modes are seamless and free of transients and subharmonic switching. the LTC3536 can be configured to operate over a wide range of switching frequencies, from 300khz to 2mhz, allowing applications to be optimized for board area and efficiency. the LTC3536 has an internal fixed-frequency oscillator with a switching frequency that is easily set by a single external resistor. in noise sensitive applications, the converter can also be synchronized to an external clock via the mode/sync pin. the operating frequency defaults to 1.2mhz when rt is connected to v in eliminating the external resistor. the LTC3536 has been optimized to reduce input current in shutdown and standby for applications that are sensi- tive to quiescent current draw, such as battery-powered devices. in burst mode operation, the no-load standby current is only 32a and in shutdown the total supply current is reduced to less than 1a. pwm m ode o pera tion with the mode/sync pin forced low or driven by an external clock, the LTC3536 operates in a fixed-frequency pulse-width modulation (pwm) mode using a voltage mode control loop. this mode of operation maximizes the output current that can be delivered by the converter, reduces out - put voltage ripple, and yields a low noise fixed-frequency switching spectrum. a proprietary switching algorithm provides seamless transitions between operating modes and eliminates discontinuities in the average inductor cur - rent, inductor current ripple, and loop transfer function throughout all regions of operation. these advantages result in increased efficiency, improved loop stability, and lower output voltage ripple in comparison to the traditional 4-switch buck-boost converter. figure 1 shows the topology of the LTC3536 power stage which is comprised of two p-channel mosfet switches and two n-channel mosfet switches and their associated gate drivers. in response to the error amplifier output, an internal pulse-width modulator generates the appropriate switch duty cycles to maintain regulation of the output voltage. sw1 v in pmos a nmos b v out pmos d nmos c 3536 f01 sw2 l figure 1. power stage schematic when the input voltage is significantly greater than the output voltage, the buck-boost converter operates in buck mode. switch d turns on continuously and switch c remains off. switch a and b are pulse-width modulated to produce the required duty cycle to support the output regulation voltage. as the input voltage decreases, switch?a remains on for a larger portion of the switching cycle. when the duty cycle reaches approximately 90% the switch pair ac begins turning on for a small fraction of the switching period. as the input voltage decreases further, the ac switch pair remains on for longer durations and the duration of the bd phase decreases proportionally. at this point, switch a remains on continuously while switch pair cd is pulse-width modulated to obtain the desired output voltage. at this point, the converter is operating solely in boost mode. oscillator and phase-locked loop the LTC3536 operates from an internal oscillator with a switching frequency that can be configured by a single external resistor between rt and ground. tying rt to v in sets the default internal operating frequency to typically 1.2mhz. if the rt pin is driven externally to a level higher than v in , a current limiting resistor should be used. 1m for 6v on the rt pin limits the current to 6a. also, a schottky
LTC3536 10 3536fa o pera t ion diode from the rt pin to v in can be used in addition to current limiting resistor. for noise sensitive applications, an internal phase-locked loop allows the LTC3536 to be synchronized to an external clock signal applied to the mode/sync pin. the free-running frequency of the oscillator can be programmed slower or faster than the synchronization clock frequency. whether operating from its internal oscillator or when synchronized to an external clock signal, the LTC3536 is able to operate with a switching frequency from 300khz to 2mhz, providing the ability to minimize the size of the external components and optimize the power conversion efficiency. error amplifier the LTC3536 has an internal high gain operational ampli - fier which provides frequency compensation of the control loop that maintains output voltage regulation. to ensure stability of this control loop, an external compensation network must be installed in the application circuit. a type iii compensation network as shown in figure 2 is recommended for most applications since it provides the flexibility to optimize the converters transient response while simultaneously minimizing any dc error in the output voltage. details on designing the compensation network in LTC3536 applications can be found in the applications information section of this data sheet. input current limit operates by injecting a current into the feedback pin, which is proportional to the extent that the inductor current exceeds the input current limit threshold (typically 2.5a). due to the high gain of the feedback loop, this injected current forces the error amplifier output to decrease until the average current through the inductor is approximately reduced to the current limit threshold. for this current limit feature to be most effective, the thevenin resistance (r bot //r top ) from fb to ground should exceed 100k. figure 2. error amplifier and compensation network + ? 0.6v fb gnd 3536 f02 LTC3536 r fb c fb c pole c ff r ff v out r top r bot vc pwm input and peak current limits the LTC3536 has two current limit circuits that are de - signed to limit the peak inductor current to ensure that the switch currents remain within the capabilities of the ic during output short-circuit or overload conditions. the current out of sw1 pin (a) 0 current fb pin (a) 11 9 13 15 1.5 2.5 4.5 3536 f03 7 5 12 10 14 8 6 3 4 1 2 0 0.5 1 2 3 43.5 figure 3. fb current for input current limitation since this input current limit circuit maintains the error amplifier in an active state it ensures a smooth recovery and minimal overshoot once the current limit fault condi - tion is removed. on a hard output short, it is possible for the inductor current to increase substantially beyond the current limit threshold before the input current limit has time to react and reduce the inductor current. for this reason, there is a second current limit circuit (peak cur - rent limit), which turns off power switch a if the current through switch a exceeds the approximately 3.4a limit threshold. this provides additional protection in the case of an instantaneous hard output short and provides time for the primary current limit to react. when the input voltage is lower than 2.4v, the input and peak current limit thresh - olds are gradually decreased. for minimum input voltage (1.8v) they are typically 1.7a and 2.3a respectively. see the typical performance characteristics and the inductor selection section for information about the inductor value for maximum output current capability.
LTC3536 11 3536fa o pera t ion reverse current limit in pwm mode operation the LTC3536 has the ability to actively conduct current away from the output if that is necessary to maintain regulation. if the output is held above regulation, this could result in large reverse currents. this situation can occur if the output of the LTC3536 is held up momentarily by another supply as may occur during a power-up or power-down sequence. to prevent damage to the part under such conditions, the LTC3536 has a reverse current comparator that monitors the current entering power switch d from the load. if this current exceeds 0.55a (typical) switch d is turned off for the remainder of the switching cycle in order to prevent the reverse inductor current from reaching unsafe levels. for no-load current application, the inductor current ripple must be lower than double the minimum reverse current limit (0.3a ? 2 = 0.6a maximum inductor current ripple). see the inductor selection section for information about how to calculate the inductor current ripple. output current capability the maximum output current that can be delivered by the LTC3536 is dependent upon many factors, the most significant being the input and output voltages. for v out = 3.3v and v in 3v, the LTC3536 is able to support a 1a load continuously. for v out = 3.3v and v in =1.8v, the LTC3536 is able to support a 300ma load continuously. typically, the output current capability is greatest when the input voltage is approximately equal to the output voltage. at larger step-up voltage ratios, the output cur - rent capability is reduced because the lower duty cycle of switch d results in a larger inductor current being needed to support a given load. additionally, the output current capability generally decreases at large step-down voltage ratios due to higher inductor current ripple which reduces the maximum attainable inductor current. the output current capability can also be affected by induc- tor characteristics. an inductor with large dc resistance will degrade output current capability, particularly in boost mode operation. in addition, larger value inductors gener - ally maximize output current capability by reducing inductor current ripple. see the typical performance characteristics and the inductor selection section for information. burst mode operation when mode/sync is held high, the buck-boost converter operates in burst mode operation using a variable frequency switching algorithm that minimizes the no-load input quiescent current and improves efficiency at light load by reducing the amount of switching to the minimum level required to support the load. the output current capabil- ity in burst mode operation is substantially lower than in pwm mode and is intended to support light stand-by loads. curves showing the maximum burst mode load current as a function of the input and output voltage can be found in the typical performance characteristics section of this data sheet. if the converter load in burst mode operation exceeds the maximum burst mode current capability, the output will lose regulation. each burst mode cycle is initiated when switches a and c turn on producing a linearly increasing current through the inductor. when the inductor current reaches the burst mode peak current limit (0.6a typically), switches b and d are turned on, discharging the energy stored in the induc- tor into the output capacitor and load. once the inductor current reaches zero, all switches are turned off and the cycle is complete. current pulses generated in this manner are repeated as often as necessary to maintain regulation of the output voltage. in burst mode operation, the error amplifier is used as burst comparator. if the mode pin is driven externally to a level higher than v in , a current limiting resistor should be used. 1m for 6v on the mode pin limits the current to 6a. also, a schottky diode from the mode pin to v in can be used in addition to current limiting resistor. s of t -s t art t o minimize input current transients on power-up, the LTC3536 incorporates an internal soft-start circuit with a nominal duration of 0.9ms. the soft-start is implemented by a linearly increasing ramp of the error amplifier refer - ence voltage during the soft-start duration. as a result, the duration of the soft-start period is largely unaffected by the size of the output capacitor or the output regula- tion voltage. given the closed-loop nature of the soft-start implementation, the converter is able to respond to load transients that occur during the soft-start interval. the
LTC3536 12 3536fa o pera t ion soft-start period is reset by thermal shutdown and uvlo events on v in and the mode of operation is always pwm. in case the output voltage at start -up is already precharged above 90% (typically) of the target value, the internal soft- start is skipped and the LTC3536 immediately enters the mode of operation that has been set on the mode pin. if the mode pin is tied high and burst mode operation is selected, the output voltage is regulated smoothly to the target voltage value. instead if the mode pin is tied low and pwm mode is selected, the error amplifier needs to charge up the vc pin and the output voltage might be pulled to lower voltage values for a short period of time, proportional to the value of the main compensation capacitor. u nder voltage l ockout t o ensure proper operation, the LTC3536 incorporates internal undervoltage lockout (uvlo) circuitry. the con - verter is disabled if v in falls below its respective uvlo threshold (typical 1.67v). if the input voltage falls below this level all switching is disabled until the input voltage rises above 1.75v (nominal). o utput d isconnect the LTC3536 is designed to allow true output disconnect by opening both p-channel mosfet rectifiers. this allows v out to go to zero volts during shutdown, drawing no current from the input source. t hermal c onsidera tions the power switches in the l tc3536 are designed to operate continuously with currents up to the internal current limit thresholds. however, when operating at high current levels there may be significant heat generated within the ic. as a result, careful consideration must be given to the thermal environment of the ic in order to optimize efficiency and ensure that the LTC3536 is able to provide its full-rated output current. specifically, the exposed pad of both the dd and msop packages shall be soldered to the pc board and the pc board should be designed to maximize the conduction of heat out of the ic package. if the die temperature exceeds approximately 165c, the ic will enter overtemperature shutdown and all switching will be inhibited. the part will remain disabled until the die cools by approximately 10c. the soft-start circuit is reinitialized in overtemperature shutdown to provide a smooth recovery when the fault condition is removed. if the shdn pin is driven externally to a level higher than v in , a current limiting resistor should be used. 1m for 6v on the shdn pin limits the current to 6a. also, a schottky diode from the shdn pin to v in can be used in addition to current limiting resistor. the standard LTC3536 application circuit is shown as the typical application on the front page of this data sheet. the appropriate selection of external components is dependent upon the required performance of the ic in each particular application given considerations and trade-offs such as pcb area, cost, output and input voltage, allowable ripple voltage, efficiency and thermal considerations. this section of the data sheet provides some basic guidelines and con- siderations to aid in the selection of external components and the design of the application circuit. a pplica t ions i n f or m a t ion inductor selection the choice of inductor used in LTC3536 application circuits influences the maximum deliverable output current, the magnitude of the inductor current ripple, and the power conversion efficiency. the inductor must have low dc series resistance or output current capability and efficiency will be compromised. larger inductance values reduce inductor current ripple and will therefore generally yield greater output current capability. for a fixed dc resistance, a larger value of inductance will yield higher efficiency by
LTC3536 13 3536fa reducing the peak current to be closer to the average out- put current and therefore minimize resistive losses due to high rms currents. however, a larger inductor within any given inductor family will generally have a greater series resistance, thereby counteracting this efficiency advantage. an inductor used in LTC3536 applications should have a saturation current rating that is greater than the worst-case average inductor current plus half the ripple current. the peak-to-peak inductor current ripple for each operational mode can be calculated from the following formula, where f is the switching frequency in mhz, l is the inductance in h. ? i l(p-p)(buck) = v out f ? l v in ? v out v in ? ? ? ? ? ? ? i l(p-p)(boost) = v in f ? l v out ? v in v out ? ? ? ? ? ? in addition to its influence on power conversion efficiency, the inductor dc resistance can also impact the maximum output capability of the buck-boost converter particularly at low input voltages. in buck mode, the output current of the buck-boost converter is limited only by the inductor current reaching the current limit threshold. however, in boost mode, especially at large step-up ratios, the output current capability can also be limited by the total resistive losses in the power stage. these include switch resis- tances, inductor resistance and pcb trace resistance. use of an inductor with high dc resistance can degrade the output current capability from that shown in the typical performance characteristics section of this data sheet. as a guideline, in most applications the inductor dc re- sistance should be significantly smaller than the typical power switch resistance of 120m. the minimum inductor value must guarantee that the worst-case average input current plus half the ripple current dont reach the input current limit threshold. for a switching frequency of 1mhz the recommended typical inductor value is 4.7h. for a higher and lower switching frequency the inductor value should be changed a pplica t ions i n f or m a t ion accordingly in order to have the same current ripple (2.2h for 2mhz, 15h for 300khz). different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. shielded construction is generally preferred as it minimizes the chances of interference with other circuitry. the choice of inductor style depends upon the price, sizing, and emi requirements of a particular application. table 1 provides a small sampling of inductors that are well suited to many LTC3536 applications. table 1. recommended inductors vendor part/style coilcraft 847-639-6400 www.coilcraft.com lpo2506 lps4012, lps4018 mss6122 mss4020 mos6020 ds1605, do1608 xpl4020 xal4040 xfl4020 coiltronics www.cooperet.com sd52, sd53 sd3114, sd311b murata 714-852-2001 www.sumida.com lqh55d sumida 847-956-0666 www.sumida.com cdh40d11 taiyo yuden www.t-yuden.com np04s8 nr3015 nr4018 tdk 847-803-6100 www.component.tdk.com vlp, ltf vlf, vlcf wrth elektronik 201-785-8800 www.we-online.com we-tpc type s, m, mh output capacitor selection a low esr output capacitor should be utilized at the buck- boost converter output in order to minimize output voltage ripple. multilayer ceramic capacitors are an excellent option as they have low esr and are available in small footprints. the capacitor value should be chosen large enough to reduce the output voltage ripple to acceptable levels.
LTC3536 14 3536fa neglecting the capacitor esr and esl, the peak-to-peak output voltage ripple can be calculated by the following formulas, where f is the frequency in mhz, c out is the capacitance in f and i load is the output current in amps. ? v (p-p)(buck) = v out 8 ? f 2 ? l ? c out v in ? v out v in ? ? ? ? ? ? ? v (p-p)(boost) = i load f ? c out v out ? v in v out ? ? ? ? ? ? given that the output current is discontinuous in boost mode, the ripple in this mode will generally be much larger than the magnitude of the ripple in buck mode. in addition to output voltage ripple generated across the output capacitance, there is also output voltage ripple produced across the internal resistance of the output capacitor. the esr-generated output voltage ripple is proportional the series resistance of the output capacitor. input capacitor selection the pv in pin carries the full inductor current and provides power to internal control circuits in the ic. to minimize input voltage ripple and ensure proper operation of the ic, a low esr bypass capacitor with a value of at least 10f should be located as close to this pin as possible. the traces connecting this capacitor to pv in and the ground plane should be made as short as possible. the sv in pin provides power to the internal circuitry. in every applica - tion, the sv in and pv in must be connected together on the pc board. recommended input and output capacitors the capacitors used to filter the input and output of the LTC3536 must have low esr and must be rated to handle the large ac currents generated by switching converters. this is important to maintain proper functioning of the ic and to reduce output voltage ripple. the choice of capacitor technology is primarily dictated by a trade-off between cost, size and leakage current. ceramic capacitors are often utilized in switching con- verter applications due to their small size, low esr and low leakage currents. however, many ceramic capacitors designed for power applications experience significant loss in capacitance from their rated value with increased dc bias voltages. for example, it is not uncommon for a small surface mount ceramic capacitor to lose more than 50% of its rated capacitance when operated near its rated voltage. as a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a higher voltage rating than required in order to actually realize the intended capacitance at the full operating voltage. to ensure that the intended capacitance is realized in the application circuit, be sure to consult the capacitor vendors curve of capacitance versus dc bias voltage. the capacitors listed in table 2 provide a sampling of small surface mount ceramic capacitors that are well suited to LTC3536 application circuits. all listed capacitors are either x5r or x7r dielectric in order to ensure that capacitance loss over temperature is minimized. table 2. representative bypass and output capacitors part number value (f) voltage (v) size (mm) l w h (footprint) avx 12066d106k 12066d226k 12066d476k 10 22 47 6.3 6.3 6.3 3.2 1.6 0.5 (1206) 3.2 1.6 0.5 (1206) 3.2 1.6 0.5 (1206) kemet c0603c106k9p c0805c226k9p c0805c476k9p 10 22 47 6.3 6.3 6.3 1.6 0.8 0.8 (0603) 2.0 1.25 1.25 (0805) 2.0 1.25 1.25 (0805) murata grm21 grm21 10 22 10 6.3 2.0 1.25 1.25 (0805) 2.0 1.25 1.25 (0805) tdk c2102x5r0j c2102x5r0j 22 47 6.3 6.3 2.0 1.25 0.85 (0805) 2.0 1.25 1.25 (0805) taiyo yuden jmk212bj jmk212bj 22 47 6.3 6.3 2.0 1.25 0.85 (0805) 2.0 1.25 0.85 (0805) small-signal model the LTC3536 uses a voltage mode control loop to maintain regulation of the output voltage. an externally compen - sated error amplifier drives the vc pin to generate the appropriate duty cycle of the power switches. use of an external compensation network provides the flexibility for optimization of closed-loop performance over the wide a pplica t ions i n f or m a t ion
LTC3536 15 3536fa figure 4. small-signal model variety of output voltages, switching frequencies, and external component values supported by the LTC3536. v in is the input supply voltage, v out the programmed output voltage, l is the external buck-boost inductor, c out the output capacitor, r s the series resistance in the power path (it can be approximated as twice the average power switch resistance plus the dc resistance of the inductor) and r c is the output capacitor esr. buck mode the small-signal transfer function of the buck-boost converter is different in the buck and boost modes of op- eration and care must be taken to ensure stability in both operating regions. when stepping down from a higher input voltage to a lower output voltage, the converter will operate in buck mode and the small-signal transfer function from the error amplifier output, v c , to the con- verter output voltage is given by the following equation: v out v c s ( ) buck mode = 2.64 ? v in ? 1 + sr c c out 1 + s o q + s o ? ? ? ? ? ? 2 this transfer function has a single zero created by the output capacitor esr and a resonant pair of poles. in most applications, an output capacitor with a very low esr is utilized in order to reduce the output voltage ripple to ac- ceptable levels. such low values of capacitor esr result in a very high frequency zero and as a result the zero is commonly too high in frequency to significantly impact compensation of the feedback loop. the denominator of the buck mode transfer function exhibits a pair of resonant poles generated by the lc out filtering of the power stage. the resonant frequency of the power stage, f o , is given by the following expression where l is the value of the inductor in henries. o = 1 lc out , f o = 1 2 lc out the quality factor, q, has a significant impact on compensa - tion of the voltage loop since a higher q factor produces a sharper loss of phase near the resonant frequency. the quality factor is inversely related to the amount of damping in the power stage and is substantially influenced by the average series resistance of the power stage, r s . lower values of r s will increase the q and result in a sharper loss of phase near the resonant frequency and will require more phase boost or lower bandwidth to maintain an adequate phase margin. q = lc out c out r c + r s ( ) + l r load boost mode when stepping up from a lower input voltage to a higher output voltage, the buck-boost converter will operate in boost mode where the small-signal transfer function from control voltage, v c , to the output voltage is given by the following expression: v out v c s ( ) boost mode = 2.64 ? g 1 + sr c c out ( ) 1? s z ? ? ? ? ? ? 1 + s o q + s o ? ? ? ? ? ? 2 in boost mode operation, the transfer function is character - ized by a pair of resonant poles and a zero generated by the esr of the output capacitor as in buck mode. however, in addition there is a right-half plane zero which generates a pplica t ions i n f or m a t ion pwm v c v in v out c out r c r load 3536 f04 a d b c l r s
LTC3536 16 3536fa increasing gain and decreasing phase at higher frequen- cies. as a result, the crossover frequency in boost mode operation generally must be set lower than in buck mode in order to maintain sufficient phase margin. g = v in ? r load r s ? 1? r s r load ? v out v in ? ? ? ? ? ? 2 1 + r load r s ? v in v out ? ? ? ? ? ? 2 o = r s + r load v in v out ? ? ? ? ? ? 2 lc out r load + r c ( ) in boost mode operation, the frequency of the right-half plane zero, f z , is given by the following expression. the frequency of the right half plane zero decreases at higher loads and with larger inductors. z = v in v out ? ? ? ? ? ? 2 r load ? r s l , f z = v in v out ? ? ? ? ? ? 2 r load ? r s 2 l finally, the magnitude of the quality factor of the power stage in boost mode operation is given by the following expression: q = lc out r load + r c ( ) r s + r load v in v out ? ? ? ? ? ? 2 l + c out r load r c v in v out ? ? ? ? ? ? 2 + r s c out r load + r c ( ) buck-boost mode when the converter operates in buck-boost mode and the small-signal transfer function from control voltage, v c , to the output voltage is given by the following expression: v out v c s ( ) buck-boost mode = 17.62 ? g 1 + sr c c out ( ) 1? s z ? ? ? ? ? ? 1 + s o q + s o ? ? ? ? ? ? 2 also in buck-boost mode operation, the transfer function is characterized by a pair of resonant poles and a zero generated by the esr of the output capacitor as in buck mode and a right half plane zero. g = 0.15 ? v out r load ? 2 ? 1.85 ? r s ? 1.85 ? ( ) ( ) ? 1.85 ? ( ) ? r s + r load ? 2 ( ) where the variable is defined: = v in ? 1.85 v out + v in o = r s + r load ? 2 lc out r load + r c ( ) in buck-boost mode operation, the frequency of the right- half plane zero, f z , is given by the following expression. the frequency of the right-half plane zero decreases at higher loads and with larger inductors. z = 1.85 ? 2 r load ? r s ? 1.85 ? ( ) l ? 1.85 ? ( ) a pplica t ions i n f or m a t ion
LTC3536 17 3536fa figure 5. buck-boost converter bode plot figure 6. error amplifier with type i compensation figure 7. error amplifier with type iii compensation finally, the magnitude of the quality factor of the power stage in buck-boost mode operation is given by the fol- lowing expression: q = lc out r load + r c ( ) r s + r load ? 2 l + c out r load r c ? 2 + r s c out r load + r c ( ) compensation of the voltage loop the small-signal models of the LTC3536 reveal that the transfer function from the error amplifier output, vc, to the output voltage is characterized by a set of resonant poles and a possible zero generated by the esr of the output capacitor as shown in the bode plot of figure 5. in boost mode operation, there is an additional right-half plane zero that produces phase lag and increasing gain at higher frequencies. typically, the compensation network is designed to ensure that the loop crossover frequency is low enough that the phase loss from the right-half plane zero is minimized. the low frequency gain in buck mode is a constant, but varies with both v in and v out in boost mode. low enough that the resultant crossover frequency of the control loop is well below the resonant frequency. in most applications, the low bandwidth of the type i com - pensated loop will not provide sufficient transient response performance. to obtain a wider bandwidth feedback loop, optimize the transient response, and minimize the size of the output capacitor, a type iii compensation network as shown in figure 7 is required. a pplica t ions i n f or m a t ion ?40db/dec ?20db/dec buck mode boost mode f rhpz 3536 f05 f o f phase ?270 ?180 ?90 0 gain for charging or other applications that do not require an optimized output voltage transient response, a simple type?i compensation network as shown in figure 6 can be used to stabilize the voltage loop. to ensure sufficient phase margin, the gain of the error amplifier must be + ? 0.6v fb gnd 3536 f06 LTC3536 c1 v out r top r bot vc + ? 0.6v fb gnd 3536 f07 LTC3536 r fb c fb c pole c ff r ff v out r top r bot vc a bode plot of the typical type iii compensation network is shown in figure 8. the type iii compensation network provides a pole near the origin which produces a very high loop gain at dc to minimize any steady-state error in the regulation voltage. two zeros located at f zero1 and f zero2 provide sufficient phase boost to allow the loop crossover frequency to be set above the resonant frequency, f o , of the power stage. the type iii compensation network also introduces a second and third pole. the second pole, at frequency f pole2 , reduces the error amplifier gain to a zero slope to prevent the loop crossover from extending too high in frequency. the third pole at frequency f pole3 provides attenuation of high frequency switching noise.
LTC3536 18 3536fa a pplica t ions i n f or m a t ion the transfer function of the compensated type iii error amplifier from the input of the resistor divider to the output of the error amplifier, vc, is: v c(s) v out(s) = g ea 1 + s 2 f zero1 ? ? ? ? ? ? 1 + s 2 f zero2 ? ? ? ? ? ? s 1 + s 2 f pole1 ? ? ? ? ? ? 1 + s 2 f pole2 ? ? ? ? ? ? the error amplifier gain is given by the following equation. the simpler approximate value is sufficiently accurate in most cases since c fb is typically much larger in value than c pole . g ea = 1 r top c fb + c pole ( ) 1 r top c fb the pole and zero frequencies of the type iii compensation network can be calculated from the following equations where all frequencies are in hz, resistances are in ohms, and capacitances are in farads. f zero1 = 1 2 r fb c fb f zero2 = 1 2 r top + r ff ( ) c ff 1 2 r top c ff f pole2 = c fb + c pole 2 c fb c pole r fb 1 2 c pole r fb f pole3 = 1 2 c ff r ff figure 9. internal loop filter in most applications the compensation network is designed so that the loop crossover frequency is above the resonant frequency of the power stage, but sufficiently below the boost mode right-half plane zero to minimize the additional phase loss. once the crossover frequency is decided upon, the phase boost provided by the compensation network is centered at that point in order to maximize the phase margin. a larger separation in frequency between the zeros and higher order poles will provide a higher peak phase boost but may also increase the gain of the error amplifier which can push out the loop crossover to a higher frequency. the q of the power stage can have a significant influence on the design of the compensation network because it determines how rapidly the 180 of phase loss in the power stage occurs. for very low values of series resistance, r s , the q will be higher and the phase loss will occur sharply. in such cases, the phase of the power stage will fall rapidly to C180 above the resonant frequency and the total phase margin must be provided by the compensation network. however, with higher losses in the power stage (larger r s ) the q factor will be lower and the phase loss will occur more gradually. as a result, the power stage phase will not be as close to C180 at the crossover frequency and less phase boost is required of the compensation network. the LTC3536 error amplifier is designed to have a fixed maximum bandwidth in order to provide rejection of switching noise to prevent it from interfering with the control loop. from a frequency domain perspective, this can be viewed as an additional single pole as illustrated in figure?9. the nominal frequency of this pole is 400khz. for typical loop crossover frequencies below about 40khz the phase contributed by this additional pole is usually figure 8. type iii compensation bode plot gain phase f zero1 f pole2 f pole3 f f zero2 90 ?90 0 ?20db/dec ?20db/dec 3536 f08 + ? internal vc c filt 3536 f09 r filt LTC3536 0.6v fb vc
LTC3536 19 3536fa figure 10. converter bode plot, v in = 1.8v, i load = 300ma a pplica t ions i n f or m a t ion negligible (for 40khz is around C5.7). however, for loops with higher crossover frequencies this additional phase lag should be taken into account when designing the compensation network. loop compensation example this section provides an example illustrating the design of a compensation network for a typical LTC3536 application circuit. in this example a 3.3v regulated output voltage is generated with the ability to supply 300ma load from an input power source ranging from 1.8v to 5.5v. to optimize efficiency 1mhz switching frequency has been chosen. in this application the maximum inductor current ripple will occur at the highest input voltage. an inductor value of 4.7h has been chosen to limit the worst-case inductor current ripple. a low esr output capacitor with a value of 22f is specified to yield a worst-case output voltage ripple of approximately 10mv (occurring at the worst-case step-up ratio and maximum load current). in summary, the key power stage specifications for this LTC3536 example application are given below: f = 1mhz v in = 1.8v to 5.5v v out = 3.3v at 300ma c out = 22f, r c = 10m l = 4.7h, r l = 60m with the power stage parameters specified, the compen - sation network can be designed. a reasonable approach is to design the compensation network at this worst-case corner and then verify that sufficient phase margin exists across all other operating conditions. in this example ap- plication, at v in = 1.8v and the full 300ma load current, the right-half plane zero will be located at 100khz and this will be a dominant factor in determining the bandwidth of the control loop. the first step in designing the compensation network is to determine the target crossover frequency for the compensated loop. this example will be designed for a 60 phase margin to ensure adequate performance over parametric variations and varying operating conditions. as a result, the target crossover frequency, f c , will be the point at which the phase of the buck-boost converter reaches C180. it is generally difficult to determine this frequency analytically, because it is significantly impacted by the q factor of the resonance in the power stage. as a result, it is best determined from a bode plot of the buck-boost converter as shown in figure 10. this bode plot is for the LTC3536 buck-boost converter using the previously speci - fied power stage parameters and was generated from the small signal model equations using ltspice ? software. in this case, the phase reaches C180 at 37.8khz making f c = 37.8khz the target crossover frequency for the com- pensated loop. from the bode plot of figure 9 the gain of the power stage at the target crossover frequency is C2db. at this point in the design process, there are three con- straints that have been established for the compensation network. it must have +2db gain at f c = 37.8khz, a peak phase boost of 60 and the phase boost must be centered at f c = 37.8khz. an analytical approach can be used to design a compensa- tion network with the desired phase boost, center frequency and gain. in general, this procedure can be cumbersome due to the large number of degrees of freedom in a type?iii compensation network. however the design process can be simplified by assuming that both compensation zeros gain (db) 30 24 18 12 6 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 1 10 100 1k 10k 100k frequency (hz) 1m 10m 100m phase (deg) ?220 ?240 3536 f10 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 gain phase v o /v c
LTC3536 20 3536fa a pplica t ions i n f or m a t ion occur at the same frequency, f z , and both higher order poles (f pole2 and f pole3 ) occur at the common frequency, f p . this is a good starting point for determining the compen - sation network. however the bode plot for the complete loop should be checked overall operating conditions and for variations in components values to ensure that suf- ficient phase margin and gain margin exists in all cases. a reasonable choice is to pick the frequency of the poles, f p , to be about 50 times higher than the frequency of the zeros, f z , which provides a peak phase boost of approxi- mately max = 60 as was assumed previously. next, the phase boost must be centered so that the peak phase occurs at the target crossover frequency. the frequency of the maximum phase boost, f c , is the geometric mean of the pole and zero: f c = f p ? f z = 50 ? f z 2 = 7 ? f z therefore, in order to center the phase boost given a factor of 50 separation between the pole and zero frequencies, the zeros should be located at one-seventh of the cross- over frequency and the poles should be located at seven times the crossover frequency as given by the following equations: f z = 1 7 ? f c = 1 7 ? 37.8khz ( ) = 5.4khz f p = 7 ? f c = 7 ? 37.8khz ( ) = 264.6khz this placement of the poles and zeros will yield a peak phase boost of 60 that is centered at the crossover frequency, f c . next, in order to produce the desired target crossover frequency, the gain of the compensation network at the point of maximum phase boost, g center , must be set to +2db. the gain of the compensated error amplifier at the point of maximum phase gain is given by: g center = 10log 2 f p 2 f z ( ) 3 r top c fb ( ) 2 ? ? ? ? ? ? ? ? assuming a multiple of 50 separation between the pole frequencies and zero frequencies this can be simplified to the following expression: g center = 20 log 50 2 f c ( ) r top c fb ( ) ? ? ? ? ? ? ? ? the first step in defining the compensation component values is to pick a value for r top that provides an accept - ably low quiescent current through the resistor divider. a value of r top = 845k is a reasonable choice. next, the value of c fb can be found: g center = 2db c fb 50 2 ? 37.8khz ( ) ? 845k ? 10 2db 20 = 198pf 180pf the compensation poles can be set at 264.6khz and the zeros at 5.4khz by using the expressions for the pole and zero frequencies given in the previous section. setting the frequency of the first zero, f zero1 , to 5.4khz results in the following value for r fb : r fb = 1 2 ? 180pf ( ) ? 5.4khz = 163k 162k this leaves the free parameter, c pole , to set the frequency f pole1 to the common pole frequency of 264.6khz as given: c pole = 1 2 ? 162k ( ) ? 264.6khz = 3.71pf 3.9pf next, c ff can be chosen to set the second zero, f zero2 , to the common zero frequency of 5.4khz. c ff = 1 2 ? 845k ( ) ? 5.4khz = 34.9pf 33pf finally, the resistor value r ff can be chosen to place the second pole at 264.6khz: r ff = 1 2 ? 33pf ( ) ? 264.6khz = 18.2k
LTC3536 21 3536fa figure 11. compensated error amplifier bode plot figure 12. complete loop bode plot for boost operation mode a bode plot of the error amplifier with the designed com - pensation component values is shown in figure 11. the bode plot confirms that the peak phase occurs at 37.8khz and the phase boost at that point is about 60. in addition, the gain at the peak phase frequency is 2db which is close to the design target. a pplica t ions i n f or m a t ion figure 13. complete loop bode plot for buck-boost operation mode gain (db) 81 72 63 54 45 36 27 18 9 0 ?9 ?18 ?27 ?36 ?45 ?54 1 10 100 1k 10k 100k frequency (hz) 1m 10m 100m ?50 ?60 ?70 ?80 ?90 3536 f11 60 50 40 30 20 10 0 ?10 ?20 ?30 ?40 phase gain v o /v c phase (deg) the final step in the design process is to compute the bode plot for the entire loop using the designed compensation network and confirm its phase margin and crossover frequency. the complete loop bode plot for this example is shown in figure 12. the loop crossover frequency is 37.8khz which matches the design target and the phase margin is approximately 60. the bode plot for the complete loop should be checked overall operating conditions and for variations in compo- nent values to ensure that sufficient phase margin and gain margin exists in all cases. the stability of the loop should also be confirmed via time domain simulation and by evaluating the transient response of the converter in the actual circuit. in this example the v in varies from 1.8v to 5.5v. in buck- boost operation (when 0.85 ? v out < v in < v out /0.85) the bode plot of the complete loop shows a phase margin of gain (db) 140 120 100 80 60 40 20 0 ?20 ?40 ?60 ?80 ?100 1 10 100 1k 10k 100k frequency (hz) v o /v c 1m 10m 100m ?240 ?260 ?280 3536 f12 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 ?220 gain phase phase (deg) 40 for v in = v out = 3.3v. in fact in this mode of operation the dc gain increase and often make this the most critical region to compensate. gain (db) 100 80 60 40 20 0 ?20 ?40 ?60 ?80 1 10 100 1k 10k 100k frequency (hz) v o /v c 1m 10m 100m ?240 ?270 3536 f13 0 ?30 ?60 ?90 ?120 ?150 ?180 ?210 phase gain phase (deg)
LTC3536 22 3536fa in order to improve the stability also in buck-boost mode of operation, the two compensation zeros could be move to different frequency: f zero2 = 1 2 r top c ff = 5.4khz f zero1 = 1 2 r fb c fb = 2 ? f zero2 = 10.8khz the new r fb value is: r fb = 1 2 ? 180pf ( ) ? 10.8khz = 81.9k 80.6k as consequence the f pole2 will move to higher frequency: f pole2 = 1 2 c pole r fb = 532khz as shown from figures 14 and 15, the stability is now improved for the buck-boost region (v in = 3v) and remains good for the boost region (v in = 1.8v). in buck mode there is no right-half plane zero and the stability is normally achieved. a pplica t ions i n f or m a t ion gain (db) 120 100 80 60 20 40 0 ?20 ?40 ?60 ?100 ?80 1 10 100 1k 10k 100k frequency (hz) v o /v c 1m 10m 100m ?240 ?260 ?280 3536 f14 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 ?220 phase gain phase (deg) figure 14. complete loop bode plot for boost operation mode figure 16. fb resistor network figure 15. complete loop bode plot for buck-boost operation mode gain (db) 140 120 100 80 40 20 60 0 ?20 ?40 ?60 ?120 ?100 ?80 1 10 100 1k 10k 100k frequency (hz) v o /v c 1m 10m 100m phase (deg) ?200 ?240 ?260 ?220 ?280 3536 f15 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 phase gain output voltage programming the output voltage is set via the external resistor divider comprised of resistors r top and r bot . the resistor divider values determine the output regulation voltage according to: v out = 0.6 1 + r top r bot ? ? ? ? ? ? v in addition to setting the output voltage, the value of r top is instrumental in controlling the dynamics of the compen- sation network. when changing the value of this resistor, care must be taken to understand the impact this will have on the compensation network. as noted in the input and peak current limit section, for current limit feature to be most effected, the thevenin resistnace (r top //r bot ) from fb to ground should exceed 100k. v out fb r top r bot 3536 f16 LTC3536
LTC3536 23 3536fa a pplica t ions i n f or m a t ion switching frequency selection higher switching frequencies facilitate the use of smaller inductors as well as smaller input and output filter capaci- tors which results in a smaller solution size and reduced component height. however, higher switching frequencies also generally reduce conversion efficiency due to the increased switching losses. in addition, the maximum voltage step-up ratio is reduced slightly at higher switching frequencies as shown in the maximum duty cycle versus switching frequency curve in the typical performance characteristics section of this data sheet. pcb layout considerations the LTC3536 buck-boost converter switches large currents at high frequencies. special attention should be paid to the pc board layout to ensure a stable, noise-free and efficient application circuit. a few key guidelines are provided: 1. the parasitic inductance and resistance of all circulating high current paths should be minimized. this can be accomplished by keeping the routes as short and as wide as possible. capacitor ground connections should via down to the ground plane by way of the shortest route possible. the bypass capacitors on pv in and v out should be placed as close to the ic as possible and should have the shortest possible paths to ground. 2. the exposed pad is the electrical power ground connec- tion for the l tc3536 in the dd package. multiple vias should connect the backpad directly to the ground plane. in addition, maximization of the metallization connected to the backpad will improve the thermal environment and improve the power handling capabilities of the ic in either package. 3. the components their connections with high current should all be placed over a complete ground plane to minimize loop cross-sectional areas. this minimizes emi and reduces inductive drops. 4. connections to all of the components with high current should be made as wide as possible to reduce the series resistance. this will improve efficiency and maximize the output current capability of the buck-boost converter 5. to prevent large cir culating currents in the ground plane from disrupting operation of the LTC3536, all small- signal grounds should return directly to gnd by way of a dedicated kelvin route. this includes the ground connection for the rt pin resistor and the ground con - nection for the feedback network. 6. keep the routes connecting to the high impedance, noise sensitive inputs fb and rt as short as possible to reduce noise pick-up. example from mode route in case the chip is synchronized with external clock.
LTC3536 24 3536fa a pplica t ions i n f or m a t ion figure 17a. fabrication layer of example pcb with 4 layers figure 17b. top layer of example pcb figure 17c. bottom layer of example pcb
LTC3536 25 3536fa typical a pplica t ions 300khz high efficiency li-ion to 3.6v at 1a, pulsed with manual mode control efficiency 3.6v, 300khz vs load current usb to 5v converter load step sw1 v in sw2 v out fb 10f v in 3v to 4.2v vc LTC3536 15h* 49.9k 332k 845k 15k 1nf mode/sync shdn rt *coilcraft xal4040 v out 3.6v 1a 169k 3536 ta02 gnd off on 47f 100f 100pf sw1 v in sw2 v out fb 2mhz external clock 47f *coilcraft xfl4020 usb power 4.3v to 5.5v vc LTC3536 2.2h* 33k 49.9k 1100k 22.6k 200pf mode/sync shdn rt v out 5v 1a 150k 3536 ta03 gnd off on 22f 18pf load current (a) 0.001 0.01 0.1 1 40 efficiency (%) 50 60 70 80 3536 ta02b 30 20 10 0 90 100 v in = 3v v in = 3.6v v in = 4.2v v out 200mv/div i load 500ma/div 100s/div 3536 ta03b v in = 4.3v v out = 5v
LTC3536 26 3536fa p ackage descrip t ion 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer msop (mse12) 0910 rev d 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev d) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3536 27 3536fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 11/11 add new bullet output disconnect in shutdown to features bullet list. in the absolute maximum ratings section change (notes 1, 2) to (note 1) and (note 2) to (notes 2, 3). in electrical characteristics table add conditions for error amplifier sink current and error amplifier source current. in pin functions add exposed pad pin 13 and remove last sentence to pgnd pin description. change negative input of peak current limit comparator to 3.4v and negative input of uvlo comparator to 1.75v. add new section output disconnect to operations section. 1 2 3 7 8 12
LTC3536 28 3536fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2011 lt 1111 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ion backup power supply sw1 v in sw2 v out fb 10f v supercap 1.8v to 5.5v vc LTC3536 4.7h* 49.9k 866k 100k 330pf 10pf mode/sync shdn rt 182k 6.04k *coilcraft xfl4020 pwm burst 6.49k 845k r2 r1 20k 20k gnd vh uv ov vl dis ltc2912-2 gnd tmr v cc 22f v sys 3.3v 300ma for v in 1.8v 1a for v in 3v 0.1f 47pf c rt 3536 ta04 main power 12v dc/dc part number description comments ltc3440 600ma (i out ) 2mhz synchronous buck-boost dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 2.5v, i q = 25a, i sd 1a, 10-lead msop and dfn packages ltc3442 1.2a (i out ) 2mhz synchronous buck-boost dc/dc converter with programmable burst mode operation v in : 2.4v to 5.5v, v out : 2.4 to 5.25v, i q = 35a, i sd 1a, dfn package ltc3444 400ma (i out ) 2mhz synchronous buck-boost dc/dc converter v in : 2.75v to 5.5v, v out : 0.5 to 5v, i q = 35a, i sd 1a, dfn package ltc3101 wide v in , multi-output dc/dc converter and powerpath? controller v in : 1.8v to 5.5v, v out : 1.5v to 5.25v, i q = 38a, i sd 15a, qfn package ltc3113 3a (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 30a, i sd < 1a, dfn and tssop packages ltc3533 2a (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 40a, i sd < 1qa, dfn package ltc3534 7v, 500ma (i out ), 1mhz synchronous buck-boost dc/dc converter 94% efficiency, v in : 2.4v to 7v, v out : 1.8v to 7v, i q = 25a, i sd < 1a, dfn and gn packages ltc3530 600ma (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 12a, i sd < 2a, qfn package ltc3112 2.5a (i out ), 15v synchronous buck-boost dc/dc converter v in : 2.7v to 15v, v out : 2.5v to 14v, i q = 40a, i sd < 1a, dfn and tssop packages ltc3127 1a (i out ), 1.2mhz synchronous buck-boost dc/dc converter with programmable input current limit 96% efficiency, v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 30a, i sd < 4a, dfn and msop packages ltc3780 high efficiency, synchronous, 4-switch buck-boost controller 98% efficiency, v in : 4v to 36v, v out : 0.8v < v out < 30v, i sd = 55a, ssop and qfn packages ltc3785 10v, high efficiency, synchronous, no r sense ? buck-boost controller 96% efficiency, v in and v out : 2.7v to 10v, i sd = 15a, i q = 86a, qfn package ltc3789 high efficiency, synchronous, 4-switch buck-boost controller 98% efficiency, v in : 4v to 38v, v out : 0.8v < v out < 38v, i sd = 40a, ssop and qfn packages

▲Up To Search▲

Price & Availability of LTC3536

	To Download LTC3536 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .